A drive substrate having TFTs and pixel electrodes on one glass substrate and a counter substrate having a common electrode and a color filter on another glass substrate are provided in a conventional TFT liquid crystal display. Further, the TFT liquid crystal panel is constituted by providing liquid crystals between these two sheets of glass substrates. The structure of the TFT is described, for example, in Japanese Examined Patent Publication No. 10955/1990.
As shown in FIG. 21, a conventional TFT liquid crystal display device includes a liquid crystal controller 201, signal drive circuits 206 and 207, a scan drive circuit 210, a power source circuit 212 and a liquid crystal panel 218. The TFT liquid crystal panel 218 has N drain buses 208 and 209 and M gate buses 211 in a matrix form. Further, pixels 219 are formed at respective intersection points. The TFT liquid crystal panel 218 has an N.times.M arrangement of the pixels 219. Each pixel 219 includes a TFT 220, a liquid crystal (capacitor) 221, an auxiliary capacitor 222, a counter electrode 223 and an auxiliary capacitor electrode 224. In FIG. 21 the liquid crystals are equivalently represented as capacitors 221. The auxiliary capacitor 222 is provided for reducing leakage current from the liquid crystal 221. In the TFT liquid crystal panel 218, an orientation state of the liquid crystal molecules is maintained by storing an electric charge in the capacitors 221 and the auxiliary capacitors 222. The TFT 220 operates as a switch for controlling charge/discharge of the electric charge to and from the capacitors 221 and 222.
The liquid crystal controller 201 controls the signal drive circuits 206 and 207 and the scan drive circuit 210 based on display data and synchronizing signals supplied from a system (not shown) via a signal bus 101. The liquid crystal controller 201 supplies the signal drive circuits 206 and 207 with liquid crystal display data and liquid crystal drive signals via signal buses 202 and 203. Further, the controller supplies various signals to the scan drive circuit 210 via a signal bus 204 and to a power source circuit 212 via a signal bus 205.
The signal drive circuits 206 and 207 supply the liquid crystal panel 218 with a drain voltage (Vd) corresponding to the liquid crystal display data via drain buses 208 and 209. A suitable circuit for the signal drive circuits 206 and 207 is disclosed in "TFT driver for VDT: HD66310 T" described in "Hitachi LCD controller/driver LSI data book (Hitachi, Ltd., semiconductor division, 1994) on pp. 933-947. In FIG. 21, a plurality of the liquid crystal controllers are used. The scan drive circuit 210 supplies the liquid crystal panel 218 with gate voltages (Vg) successively selecting the pixels of one horizontal line via a gate bus 211.
The power source circuit 212 supplies the different voltages necessary for driving the liquid crystal panel 218 to the above-described portions. The power source circuit 212 supplies power source voltages to the scan drive circuit 210 via a power source bus 213 and to the respective signal drive circuits 206 and 207 via power source buses 214 and 215. Further,the power source circuit 212 supplies counter electrode voltages (Vcom) to counter electrodes 223 via a power source bus 216 and auxiliary capacitor voltages (Vstg) to auxiliary capacitor electrodes 224 via a power source bus 217.
A specific structure of the pixel 219 of FIG. 21 is described with reference to FIG. 22 and FIG. 23. As shown in FIG. 22 the liquid crystal panel 218 is constituted by glass substrates 401 and 402, polarizing films 403 and 404, orientation films 405 and 406, an insulating film 407 and liquid crystal molecules 408. Further, the liquid crystal panel includes the TFTs 220 and the counter electrodes 223. The liquid crystal molecules 408 have a twist structure as shown in FIG. 22 by the orientation control of the orientation films 405 and 406. The insulating film 407 disposed between the pixel electrode 303 and the auxiliary capacitor electrodes 224 operates as the above-described auxiliary capacitor 222. The TFT 220 is provided on the glass substrate 402 and the counter electrode 223 is provided on the glass substrate 401.
As shown in FIG. 23, the TFT 220 includes a silicon portion 301, a source electrode 302, a pixel electrode 303, a gate electrode and a drain electrode. The gate electrode is constituted by a gate line Gm of the gate bus 211 and the drain electrode is constituted by a drain line Dn of the drain bus 208.
FIG. 24 illustrates a voltage/brightness characteristic of a liquid crystal. The abscissa designates a voltage value applied on the liquid crystal and the ordinate designates a brightness. In FIG. 24 the following notations are utilized.
Vcen: Reference voltage value (equivalent to counter electrode voltage Vcom in FIGS. 25(a) and 25(b)); PA1 VdB1: Voltage level performing negative black display; PA1 VdW1: Voltage level performing negative white display; PA1 VdW2: Voltage level performing positive white display; and PA1 VdB2: Voltage level performing positive black display. PA1 Vg (m): Voltage waveform of gate line GM; PA1 Vd (n): Voltage waveform of drain line Dn; PA1 Vd (n+1): Voltage waveform of drain line Dn+1; PA1 Vs(m)(n): Waveform of pixel electrode voltage (hereinafter, "source voltage") applied on the pixel 219 at the m-th row and n-th column; and PA1 Vs(m)(n+1): Waveform of source voltage applied on the pixel 219 at the m-th row and (n+1)-th column.
FIGS. 25(a) and 25(b) illustrate drive voltage waveforms of a liquid crystal panel in a case where the reference voltage (Vcen) is regarded as the counter electrode voltage (Vcom) and the auxiliary capacitor electrode voltage(Vstg).
The following notations are utilized in FIGS. 25(a) and 25(b).
In operation of the conventional liquid crystal display device, the liquid crystal controller 201 converts display data and synchronizing signals transmitted through the signal bus 201 into liquid crystal display data and liquid crystal drive signals for driving the TFT liquid crystal panel 218. Further, the liquid crystal drive signals after conversion are supplied to the signal drive circuits 206 and 207 via the respective signal buses 202 and 203 and are further supplied to the scan drive circuit 210 via the signal bus 204. Additionally, predetermined signals are supplied to the power source circuit 212 via the signal bus 205.
The signal drive circuits 206 and 207 successively receive the liquid crystal display data sent via the signal buses 202 and 203 and form drain voltages corresponding to the liquid crystal display data. At this occasion, when the liquid crystal display data of one horizontal line have been received, the signal drive circuits 206 and 207 simultaneously output the drain voltages corresponding to the liquid crystal display data of the one horizontal line to the drain buses 208 and 209 in synchronism with the synchronizing signals sent in a similar manner. The signal drive circuits 206 and 207 continue outputting the drain voltages during the one horizontal period. In parallel with outputting of the drain voltages, the signal drive circuits 206 and 207 successively receive the liquid crystal display data of a next line. By repeating this operation during one frame period, the signal drive circuits 206 and 207 form the drain voltages corresponding to the liquid crystal display data of the one frame.
In the liquid crystal panel 218, a twist angle of the liquid crystal molecules 408 present in the pixel portion, that is, the transmittance of the pixel is changed by controlling the electric field with regard to each pixel. The electric field control is performed by controlling a voltage difference (potential difference) between the drain voltage (Vd) applied on the pixel electrode 303 and the voltage (Vcom) applied on the counter electrode 223. As shown in FIG. 24, when the reference voltage (Vcen) is considered as a reference, the transmittance is lowered and the pixel becomes dark when the applied voltage difference is large. However, the transmittance is promoted and the pixel becomes bright when the applied voltage difference is small.
The application of the drain voltage Vd on the pixel electrode 303 is effected by successively applying a select voltage on the gate bus 211 by the scan drive circuit 210 in synchronism with outputting the drain voltage Vd to the drain buses 208 and 209 by the signal drive circuits 206 and 207. When an ON voltage (vgon) is applied on the gate line Gm, the drain voltages (Vd (n),Vd (n+1)) supplied to the drain lines Dn, D(n+1) are applied on the pixel electrode 303 at the m-th column via the TFT 220. As a result the drain voltages (Vd(n), Vd(n+1)) applied at this time become th source voltages (Vs(m) (n), Vs (m) (n+1)). An electric charge of an amount corresponding to the source voltages (Vs(m) (n), Vs(m) (n+1)) is stored in the liquid crystal (capacitor 221) and the auxiliary capacitor 222.
The liquid crystal panel 218 is significantly deteriorated when the same voltage is continuously applied. Therefore, the deterioration of the liquid crystal panel 218 is prevented by changing the polarity of the drain voltage Vd (alternating current drive) at every constant period ( for example, one frame). The brightness of the liquid crystal panel 218 remains the same irrespective of whether the polarity of the drain voltage is positive or negative if the effective value of the difference between the drain voltage (Vd) and the reference voltage (vcen) stays the same. Accordingly, it is possible to perform the display by alternating current driving.
The counter electrodes 223 are arranged on the side of the glass substrate 401 in the liquid crystal panel 218 and therefore, all the pixels 219 included in one row share one counter electrode 223 (in other words, the electric potentials of the counter electrodes 223 become the same). Similarly, all the pixels 219 included in one column share a drain line (in other words, the potentials of the drain electrodes become the same). Therefore, the generation of flicker is prevented by changing the polarities of the drain voltages Vd at every contiguous pixel 219. When the positive drain voltage (for example, VdB2) is applied on the drain lines Dn at odd number columns, a negative drain voltage (for example, VdB1) is applied on the drain lines D(n+1) at even number columns.
It is necessary for the signal drive circuits 206 and 207 to have a capacity for generating both the positive drain voltage (VdB2) and the negative drain voltage (VdB1) to obtain the above-described drive system. Therefore, the voltage resistance capability required for the signal drive circuits 206 and 207 becomes greater. For example, assuming a case in which the potential difference between the drain voltages VdB1 and VdW1 is a voltage level (approximately 5 V) of a general purpose logic circuit, a voltage resistance capability of 10 V or more is necessary for the signal drive circuits 206 and 207. As a result, the price of the signal drive circuits 206 and 207 or the price of the liquid crystal display device is increased.